1. Field of the Invention
This invention relates to a random access memory arrangement for a semiconductor memory device, and particularly to a 1-MIS transistor-1-capacitor type semiconductor memory device which has improved integration density by employing folded bit lines.
2. Description of the Prior Art
The 1-MOS transistor-1-capacitor type random access memory (RAM) is roughly classified, normally, into two types in accordance with the arrangement of the pairs of bit lines connected to the sense amplifiers. The memory of the first type has an arrangement where each of a pair of bit lines of the bit line pair are on opposite sides of the sense amplifier and run away from the sense amplifier in right and left directions respectively. The prior art reference, U.S. Pat. No. 4,012,757 discloses such a memory. The memory of the second type has an arrangement where a pair of bit lines run in parallel with each other away from the sense amplifier in only one direction. The prior art reference, U.S. Pat. No. 4,044,340 discloses such a second type of memory.
The RAM of the 1-transistor-1-capacitor type comprises a plurality of memory cells each having a capacitor for storing data and a transfer transistor for electrically connecting the capacitor to the bit lines. Readout of data is carried out as explained below. Charges stored in the capacitors of selected memory cells are transferred to the bit lines, the potential of bit lines is amplified by the sense amplifier and then the signal obtained is transferred to the outside via the bus line.
The RAM of this type is required to have capacitors having a large capacitance for each memory cell in order to realize an error-less readout of data and a long refresh time. However, when the memory is required to have a large information storage capacity, the capacitors tend to occupy less area. Therefore, it has normally been a contradictory requirement for the 1-transistor-1-capacitor type RAM to realize both large capacity storage and error-less readout of data with a long log refresh time.